| 1 | High-Speed and Low-Cost In-Array Memristive Multipliers using SIXOR and TMSL Logics | Roya Rahimi Disfani, Mojtaba Valinataj, Nima TaheriNejad | IEEE TRANSACTIONS ON NANOTECHNOLOGY | 2026 |
| 2 | High-speed binary coded decimal digit multipliers with multiple error detection | Zahra Yazdanian amiri, Mojtaba Valinataj | INTEGRATION-THE VLSI JOURNAL | 2023 |
| 3 | Hierarchical multipliers: A framework for high-speed multiple error detecting architectures | Mojtaba Valinataj, Axel Jantsch | MICROELECTRONICS JOURNAL | 2022 |
| 4 | High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic | Maytham Allahi roodpoushti, Mojtaba Valinataj | INTEGRATION-THE VLSI JOURNAL | 2021 |
| 5 | Comments on "Improved designs of digit-by-digit decimal multiplier" | Mojtaba Valinataj, Zahra Yazdanian amiri | INTEGRATION-THE VLSI JOURNAL | 2021 |
| 6 | An Enhanced Self-checking Carry Select Adder Utilizing the Concept of Self-checking Full Adder | Mojtaba Valinataj | International Journal of Engineering | 2021 |
| 7 | Parloom: A New Low-Power Set-Associative Instruction Cache Architecture Utilizing Enhanced Counting Bloom Filter and Partial Tags | Sajjad Rostami Sani, Mojtaba Valinataj, Saeideh Alinezhad | JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS | 2019 |
| 8 | Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters | Mojtaba Valinataj | MICROELECTRONICS RELIABILITY | 2019 |
| 9 | Reversible Logic Multipliers: Novel Low-cost Parity-Preserving Designs | Farshid Eslami Chalandar, Mojtaba Valinataj, Hamid Jazayeri | International Journal of Engineering | 2019 |
| 10 | A low-cost high-speed self-checking carry select adder with multiple-fault detection | Mojtaba Valinataj, Abbas Mohammadnezhad, Jari Nurmi | MICROELECTRONICS JOURNAL | 2018 |
| 11 | aPaRT A Fast Meta-Heuristic Algorithm using Path-Relinking and Tabu Search for Allocating Machines to Operations in FJSP Problem | Sahar Bakhtar, Hamid Jazayeri, Mojtaba Valinataj | Inteligencia Artificial | 2018 |
| 12 | Novel parity-preserving reversible logic array multipliers | Mojtaba Valinataj | JOURNAL OF SUPERCOMPUTING | 2017 |
| 13 | A Novel Reduced-Precision Fault-Tolerant Floating-Point Multiplier | Maryam Mohajer, Mojtaba Valinataj | International Journal of Modern Education and Computer Science | 2017 |
| 14 | Triple tooth AlGaN/GaN HEMT on SiC substrate A novel structure for high-power applications | Majid Ghaffari, Ali A. Orouji, Mojtaba Valinataj | JOURNAL OF THE KOREAN PHYSICAL SOCIETY | 2017 |
| 15 | Novel low-cost and fault-tolerant reversible logic adders | Mojtaba Valinataj, , Hamid Jazayeri | COMPUTERS and ELECTRICAL ENGINEERING | 2016 |
| 16 | A low-cost fault-tolerant and high-performance router architecture for on-chip networks | Mojtaba Valinataj, Mostafa Shahiri Tabarestani | MICROPROCESSORS AND MICROSYSTEMS | 2016 |
| 17 | Fault-tolerant carry look-ahead adder architectures robust to multiple simultaneous errors | Mojtaba Valinataj | MICROELECTRONICS RELIABILITY | 2015 |
| 18 | A novel self-checking carry lookahead adder with multiple error detection/correction | Mojtaba Valinataj | MICROPROCESSORS AND MICROSYSTEMS | 2014 |
| 19 | Reliability and Performance Evaluation of Fault-aware Routing Methods for Network-on-Chip Architectures | Mojtaba Valinataj | International Journal of Engineering, Transactions A: Basics | 2014 |
| 20 | A reconfigurable and adaptive routing method for fault-tolerant mesh-based networks-on-chip | Mojtaba Valinataj, Siamak Mohammadi, Juha Plosila, Pasi Liljeberg, Hannu Tenhunen | AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS | 2011 |
