| 21 | High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic | Maytham Allahi roodpoushti, Mojtaba Valinataj | INTEGRATION-THE VLSI JOURNAL | 2021 |
| 22 | An Enhanced Self-checking Carry Select Adder Utilizing the Concept of Self-checking Full Adder | Mojtaba Valinataj | International Journal of Engineering | 2021 |
| 23 | Comments on "Improved designs of digit-by-digit decimal multiplier" | Mojtaba Valinataj, Zahra Yazdanian amiri | INTEGRATION-THE VLSI JOURNAL | 2021 |
| 24 | High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic | Maytham Allahi roodpoushti, Mojtaba Valinataj | INTEGRATION-THE VLSI JOURNAL | 2021 |
| 25 | Comments on "Improved designs of digit-by-digit decimal multiplier" | Mojtaba Valinataj, Zahra Yazdanian amiri | INTEGRATION-THE VLSI JOURNAL | 2021 |
| 26 | An Enhanced Self-checking Carry Select Adder Utilizing the Concept of Self-checking Full Adder | Mojtaba Valinataj | International Journal of Engineering | 2021 |
| 27 | High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic | Maytham Allahi roodpoushti, Mojtaba Valinataj | INTEGRATION-THE VLSI JOURNAL | 2021 |
| 28 | High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic | Maytham Allahi roodpoushti, Mojtaba Valinataj | INTEGRATION-THE VLSI JOURNAL | 2021 |
| 29 | High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic | Maytham Allahi roodpoushti, Mojtaba Valinataj | INTEGRATION-THE VLSI JOURNAL | 2021 |
| 30 | Comments on "Improved designs of digit-by-digit decimal multiplier" | Mojtaba Valinataj, Zahra Yazdanian amiri | INTEGRATION-THE VLSI JOURNAL | 2021 |
| 31 | An Enhanced Self-checking Carry Select Adder Utilizing the Concept of Self-checking Full Adder | Mojtaba Valinataj | International Journal of Engineering | 2021 |
| 32 | An Enhanced Self-checking Carry Select Adder Utilizing the Concept of Self-checking Full Adder | Mojtaba Valinataj | International Journal of Engineering | 2021 |
| 33 | Comments on "Improved designs of digit-by-digit decimal multiplier" | Mojtaba Valinataj, Zahra Yazdanian amiri | INTEGRATION-THE VLSI JOURNAL | 2021 |
| 34 | High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic | Maytham Allahi roodpoushti, Mojtaba Valinataj | INTEGRATION-THE VLSI JOURNAL | 2021 |
| 35 | An Enhanced Self-checking Carry Select Adder Utilizing the Concept of Self-checking Full Adder | Mojtaba Valinataj | International Journal of Engineering | 2021 |
| 36 | Comments on "Improved designs of digit-by-digit decimal multiplier" | Mojtaba Valinataj, Zahra Yazdanian amiri | INTEGRATION-THE VLSI JOURNAL | 2021 |
| 37 | Reversible Logic Multipliers: Novel Low-cost Parity-Preserving Designs | Farshid Eslami Chalandar, Mojtaba Valinataj, Hamid Jazayeri | International Journal of Engineering | 2019 |
| 38 | Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters | Mojtaba Valinataj | MICROELECTRONICS RELIABILITY | 2019 |
| 39 | Parloom: A New Low-Power Set-Associative Instruction Cache Architecture Utilizing Enhanced Counting Bloom Filter and Partial Tags | Sajjad Rostami Sani, Mojtaba Valinataj, Saeideh Alinezhad | JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS | 2019 |
| 40 | Parloom: A New Low-Power Set-Associative Instruction Cache Architecture Utilizing Enhanced Counting Bloom Filter and Partial Tags | Sajjad Rostami Sani, Mojtaba Valinataj, Saeideh Alinezhad | JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS | 2019 |
