| 1 | High-Speed and Low-Cost In-Array Memristive Multipliers using SIXOR and TMSL Logics | Roya Rahimi Disfani, Mojtaba Valinataj, Nima TaheriNejad | IEEE TRANSACTIONS ON NANOTECHNOLOGY | 2025 |
| 2 | High-Speed and Low-Cost In-Array Memristive Multipliers using SIXOR and TMSL Logics | Roya Rahimi Disfani, Mojtaba Valinataj, Nima TaheriNejad | IEEE TRANSACTIONS ON NANOTECHNOLOGY | 2025 |
| 3 | High-Speed and Low-Cost In-Array Memristive Multipliers using SIXOR and TMSL Logics | Roya Rahimi Disfani, Mojtaba Valinataj, Nima TaheriNejad | IEEE TRANSACTIONS ON NANOTECHNOLOGY | 2025 |
| 4 | High-Speed and Low-Cost In-Array Memristive Multipliers using SIXOR and TMSL Logics | Roya Rahimi Disfani, Mojtaba Valinataj, Nima TaheriNejad | IEEE TRANSACTIONS ON NANOTECHNOLOGY | 2025 |
| 5 | High-Speed and Low-Cost In-Array Memristive Multipliers using SIXOR and TMSL Logics | Roya Rahimi Disfani, Mojtaba Valinataj, Nima TaheriNejad | IEEE TRANSACTIONS ON NANOTECHNOLOGY | 2025 |
| 6 | High-Speed and Low-Cost In-Array Memristive Multipliers using SIXOR and TMSL Logics | Roya Rahimi Disfani, Mojtaba Valinataj, Nima TaheriNejad | IEEE TRANSACTIONS ON NANOTECHNOLOGY | 2025 |
| 7 | High-speed binary coded decimal digit multipliers with multiple error detection | Zahra Yazdanian amiri, Mojtaba Valinataj | INTEGRATION-THE VLSI JOURNAL | 2023 |
| 8 | High-speed binary coded decimal digit multipliers with multiple error detection | Zahra Yazdanian amiri, Mojtaba Valinataj | INTEGRATION-THE VLSI JOURNAL | 2023 |
| 9 | High-speed binary coded decimal digit multipliers with multiple error detection | Zahra Yazdanian amiri, Mojtaba Valinataj | INTEGRATION-THE VLSI JOURNAL | 2023 |
| 10 | High-speed binary coded decimal digit multipliers with multiple error detection | Zahra Yazdanian amiri, Mojtaba Valinataj | INTEGRATION-THE VLSI JOURNAL | 2023 |
| 11 | High-speed binary coded decimal digit multipliers with multiple error detection | Zahra Yazdanian amiri, Mojtaba Valinataj | INTEGRATION-THE VLSI JOURNAL | 2023 |
| 12 | High-speed binary coded decimal digit multipliers with multiple error detection | Zahra Yazdanian amiri, Mojtaba Valinataj | INTEGRATION-THE VLSI JOURNAL | 2023 |
| 13 | Hierarchical multipliers: A framework for high-speed multiple error detecting architectures | Mojtaba Valinataj, Axel Jantsch | MICROELECTRONICS JOURNAL | 2022 |
| 14 | Hierarchical multipliers: A framework for high-speed multiple error detecting architectures | Mojtaba Valinataj, Axel Jantsch | MICROELECTRONICS JOURNAL | 2022 |
| 15 | Hierarchical multipliers: A framework for high-speed multiple error detecting architectures | Mojtaba Valinataj, Axel Jantsch | MICROELECTRONICS JOURNAL | 2022 |
| 16 | Hierarchical multipliers: A framework for high-speed multiple error detecting architectures | Mojtaba Valinataj, Axel Jantsch | MICROELECTRONICS JOURNAL | 2022 |
| 17 | Hierarchical multipliers: A framework for high-speed multiple error detecting architectures | Mojtaba Valinataj, Axel Jantsch | MICROELECTRONICS JOURNAL | 2022 |
| 18 | Hierarchical multipliers: A framework for high-speed multiple error detecting architectures | Mojtaba Valinataj, Axel Jantsch | MICROELECTRONICS JOURNAL | 2022 |
| 19 | High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic | Maytham Allahi roodpoushti, Mojtaba Valinataj | INTEGRATION-THE VLSI JOURNAL | 2021 |
| 20 | Comments on "Improved designs of digit-by-digit decimal multiplier" | Mojtaba Valinataj, Zahra Yazdanian amiri | INTEGRATION-THE VLSI JOURNAL | 2021 |
